In: The Journal of VLSI Signal Processing, Volume 43, 2, 2006, pages 223-233. June 2006. URL: http://dx.doi.org/10.1007/s11265-006-7272-4.
Abstract: This paper presents an approach utilizing deterministic and stochastic Petri nets (DSPN) to analyze on-chip communication. In order to demonstrate the suitability of this approach, the on-chip communication structure of two examples featuring typical system-on-chip (SoC) communication conflicts like competition for common communication resources have been studied. A state-of-the-art heterogeneous digital signal processor (DSP) and a design example with an on-chip bus have been examined. The results show that sufficient modeling accuracy can be achieved with low modeling effort in terms of computation and implementation time.
Keywords: Petri nets; SoC communication; performance estimation; performance modeling; design space exploration.
Back to the Petri Nets Bibliography