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Deriving signal transition graphs from behavioral Verilog HDL.

Blunno, I.; Lavagno, L.

In: Proc. 2nd Workshop on Hardware Design and Petri Nets (HWPN'99) of the 20th Int. Conf. on Application and Theory of Petri Nets (PN'99), 21 June 1999, Williamsburg, VA, pages 113-129. 1999.

Also in: Yakovlev, A.; Gomes, L.; Lavagno, L.: Hardware Design and Petri Nets, pages 151-170. Boston: Kluwer Academic Publishers, 2000.

Abstract: We propose a design flow for asynchronous circuits that closely mimics the standard synchronous ASIC design flow. Key elements of the flow are HDL-based specification, logic synthesis and physical design. In this work we present a proposal for using a standard HDL, Verilog, to specify an asynchronous control circuit at the behavioral level. This specification is automatically translated in a Signal Transition Graph, that can then be automatically synthesized by existing tools. Advantages of this methodology include rapid path to implementation, re-use of simulation patterns, between pre- and post-synthesis steps, and designer familiarity with the specification language.

Keywords: Verilog HDL, asynchronous circuit design, signal transition graphs, synchronous circuit design.

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