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Petri net Based Modelling, Analysis and Simulation of Pipelined Architectures.

Briz, J.L.; Colom, J.M.; Vinals, V.

In: Proceedings of the P.D. COM'91 IMACS-IFAC International Symposium on Parallel and Distributed Computing in Engineering Systems, Kanoni, Corfu, Greece, pages 37-38. 1991.

Abstract: This work discusses the use of Generalized and Coloured Petri nets to model features of existing parallel architectures, to analyze proposed designs, and to investigate and evaluate changes which will increase, in general, the parallellism of the end product. We have considered a load/store architecture based on MIPS, with an instruction set of six basic instructions, two addressing modes (register-register and register-inmediate) and three instruction formats. A five stage reservation table was also established over an elementary organization based on: an Instruction Register, two memory interface registers, an ALU with an output and two input registers, one condition flag, a Program counter with an incrementer, two read-buses and one write-bus over the Register file, and a decoding and control unit. Our architecture lacks interlock detection and internal forwardings, and the compiler is assumed to insert nop instructions to avoid data hazards. Structural hazards are excluded due to the organization and the adopted pipelining.

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