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Penelope: A Graph Based Logic Simulator for MOS Circuits.

Castagnolo, B.; Corsi, F.; Martino, S.

In: Proceedings of the IEEE International Symposium on Circuits and Systems, pages 1365-1368. New York: IEEE, 1988.

Abstract: A logic simulation tool called PENELOPE (Petri net logic performance evaluator) with precise delay estimation capabilities is presented. The simulator makes use of a description of the logic network in terms of a Petri-net-like graph which implements the truth table of each logic operator and also processes the property of describing the evolution of the signal transitions in the network.

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