In: IEICE Trans. on Fundamentals in Electronics, Communications and Computer Science, Vol. E78-A, No. 11, pages 1511-1518. 1995.
Abstract: This paper proposes a hardware architecture of a programmable controller based on Petri nets. The suggested architecture archives sufficiently rapid processing even as demands on PCs become increasingly complex. The architecture's speed and efficiency are derived from an automatic and dynamic superscalar computing capability that executes bit instructions and data handling instructions simultaneously without preprocessing, due to the properties of Petri nets. Specific characteristics for both architectural memory-based implementation of Petri net and evolution algorithms are suggested and classified by the net structure. Analysis of the suggested architectures and effects on performance are also given with mathematical formulas and a computer simulation.
Keywords: Petri nets, programmable controllers, sequence control, superscalar architectures.
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