In: ICSI'90. Proceedings of the First International Conference on Systems Integration, 1990, Morristown, NJ, USA, pages 63-73. Piscataway, NJ, USA: IEEE Service Center, 1990.
Abstract: Consideration is given to the performance analysis of a RISC (reduced instruction set computer) machine (RISC/B) based on timed Petri net (TPN) models. The operation flow graph is created according to the RISC/B instruction execution patterns and the pipeline structures. A TPN is used to model the operation in the graph. A sequence of discrete-time Markov chains (DTMCs) is built from the TPN in the instruction execution path. The model has been validated by comparing the analytical results with those obtained from the RISC/B prototype machine. Bottlenecks in the prototype have been identified through the model.
Keywords: (modelling and) performance evaluation (of) RISC/B processor; reduced instruction set computer; pipeline structure; timed net; operation flow graph; discrete-time Markov chain.
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