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Logic Simulation with Interval-Labelled Net Model.

Chiu, Peter P.K.; Cheung, Y.S.

In: PNPM89. Proceedings of the Third International Workshop On Petri Nets and Performance Models, 1989, Kyoto, Japan, pages 132-141. Los Alamitos, CA, USA: IEEE Computer Society Press, 1990.

Abstract: A novel approach in the application of interval-labelled net model in logic simulation with timing among concurrent processes is introduced. By means of the interval-labelled net model, logic circuit properties involving timing information can be specified and simulated in a multiprocessor-based environment using the token passing algorithm. The structure of a logic simulator with timing information is proposed by adopting this approach.

Keywords: logic simulation; interval-labelled net; multiprocessor-based environment.

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