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Performance analysis of 4 memory consistency models for multithreaded multiprocessors.

Chong, Y.-K.; Hwang, K.

In: IEEE Trans. on Parallel and Distributed Systems, Vol. 6, No. 10, pages 1085-1099. 1995.

Abstract: Stochastic timed Petri nets are developed to evaluate the relative performance of distributed shared memory models for scalable multiprocessors, using multithreaded processors as building blocks. Four shared memory models are evaluated: the Sequential Consistency (SC) model by Lamport (1979), the Weak Consistency (WC) model by Dubois et al, (1986), the Processor Consistency (PC) model by Goodman (1989), and the Release Consistency (RC) model by Gharachorloo et al, (1990). We assumed a scalable network with a sufficient bandwidth to absorb the increased traffic from multithreading, coherent caches, and memory event reordering, The embedded Markov chains are solved to reveal the performance attributes, Under saturated conditions, we find that multithreading contributes more than 50% of the performance improvement, while the improvement from memory consistency models varies between 20% to 40% of the total performance gain, Petri net models are effective to predict the performance of processors with a larger number of contexts than that can be simulated in previous benchmark studies. The accuracy of these memory performance models was validated with the simulation results from Stanford University. Our analytical results reveal the lowest performance of the SC model amongst four memory consistency models, The PC model requires to use larger write buffers, while the WC and RC models require smaller write buffers. The PC model may perform even lower than the SC model, if a small buffer was used, The performance of the WC model depends heavily on the synchronization rate in user code. For a low synchronization rate, the WC model performs as well as the RC model, With sufficient multithreading and network bandwidth, the RC model shows the best performance among the four models, Furthermore, we discovered that cache interferences cause very little performance degradation in all relaxed memory consistency models; as long as the network is contention-free even when multithreading has saturated the system.

Keywords: distributed shared memory, memory consistency models, stochastic Petri nets.

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