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Impact of leaky bucket regulation on the performance of combined I/O buffering in ATM switches.

Day, Khaled; Shihab, Khalil; ben Mnaouer, Adel

In: Proceedings of the second IEEE International Conference on Systems, Man and Cybernetics (SMC'02), October 6-9, 2002, Hammamet, Tunisia, Volume 1. IEEE Computer Society Press, October 2002.

Abstract: We propose a colored Petri net (CPN) model used for prototyping and modeling a complex switching scheme for ATM switches based on the combined I/O buffering technique. The new scheme that was proposed recently in the literature is evaluated here within an overall setting that includes the traffic regulations enforced by the leaky bucket algorithm. The new scheme is based on splitting the traffic coming into input lines into two priority queues (high and low) where traffic destined to busy ports is directed to the low priority queue. This scheme was compared against pure combined I/O buffering and simulation results showed that the new scheme pays back in decreasing transmission delay only when the traffic increases beyond a certain level. In addition the sensitivity analysis of the bucket size showed also that this latter affects the performance of the system only at high loads.

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