In: 16th Symposium on Integrated Circuits and Systems Design (SBCCI'03), September 08 - 11, 2003, São Paulo, Brazil, pages 131-136. IEEE Press, September 2003.
Abstract: System on a Chip (SoC) has become a reality, facing design of complex circuits into a single programmable device, supporting different cores for microprocessors, interface, bus, etc. However, the automatic inclusion of new general cores from different providers via a standard bus still needs a reliable interface mechanism to guarantee the correct protocol conversion and performance. This work presents a CAD tool to cope this problem based on a Petri Net protocol conversion approach in a high level behavioral specification, focusing on bus planning and core integration.
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