In: IEEE Micro, Vol. 11, No. 2, pages 20-23, 56-64. April 1991.
Abstract: An efficient simulator of Petri nets, suitable for both loosely and tightly coupled parallel systems and featuring high-execution speed, is proposed. This speed is obtained through an optimized software structure on an original hardware architecture that is based on digital signal processors of the TMS320 family. The Petri net class outlined compactly represents a wide range of processes by restricting the model size and the relevant simulation times. The simulation algorithm and simulator implementation are described.
Keywords: net simulation tool; digital signal processor.
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