In: Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1989, Cambridge, MA, USA, pages 212-216. Piscataway, NJ, USA: IEEE Service Center, 1989.
Abstract: Asynchronous designs are of increasing interest because of the cost of broadcasting clocks over large areas of a chip. A tool for comparing implementations of speed-independent circuits with specifications is described. Petri nets are used throughout as a user-level description language. These are translated into trace structures, which can then be processed by an existing automatic verifier. This tool is applied to a nontrivial self-timed queue design.
Keywords: automatic verification (of) speed-independent circuit; net (as) user-level description language; trace structure; self-timed queue design; verification tool.
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