In: Proceedings of the IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pages 277-280. 1995.
Abstract: Systems are constructed by connecting simpler modules. Interfaces are used to achieve inter-module connectivity. This work addresses the problem of verifying the correctness of the interface timed behavior in advance of its implementation. A technique called timing analysis for synthesis (TAFS) models the interface path delays as random variables and finds the tights bounds on those variables which satisfy the timing constraints given in the specifications. Such model allows the designer to perform a reliability analysis in addition to finding bounds on the timing parameters of the interface design.
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