In: Power-Aware Computer Systems : Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002. Revised Papers, pages 130-140. Volume 2325 of Lecture Notes in Computer Science, January 2003.
Abstract: Modern DRAM technologies offer power management features for optimization between performance and energy consumption. This paper employs Petri nets to model and evaluate memory controller policies for manipulating multiple power states. The model has been validated against the analysis and simulation used in our previous work. We extend it to model more complex policies and our results show that DRAM chip should always immediately transition to standby and never transition to powerdown provided that it exhibits typical exponential access behavior.
Keywords: Control Policy; DRAM; Memory Controller; Modeling; Petri Nets.
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