In: First ACM and IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE'03), Mont Saint-Michel, France, pages 172-182. IEEE, June 2003.
Abstract: The functioning of the computer as a control component within a larger overall application, as in the embedded systems, may affect the application's integrity as well as people and equipment involved by the application. A computer like any physical system is subject to failure with consequences ranging from inconvenience to catastrophe. This paper proposes high level models for fault tolerant mechanisms, in special TMR and recovery block, based on deterministic and stochastic Petri net (DSPN). By means of the proposed models it is possible to perform preliminary reliability analysis and the obtained results might be considered in a co-design methodology. The proposed approach allows the modeler to calculate the reliability of a fault tolerant embedded systems as a function of the failure rate. In this paper this feature is extended to allow for the determination of the reliability combining a range of failure rates.