In: Proc. 1998 Int. Verilog HDL Conf. and VHDL Int. User Forum, 16-19 March 1998, Santa Clara, CA, pages 188-194. 1998.
Abstract: In this paper, the signal transition graph (STG) model (which can be viewed as an interpreted Petri net, and which is a specification forum that is widely used for asynchronous circuits' behavior specification) is extended to include the delay information. Timed STG models and their firing semantics are defined. An automatic technique for timed STG behavior specification in VHDL is also presented. The resulting VHDL description may be used to simulate the STG behavior with the specified delays. The requirements imposed on the STG to allow the joint environment - circuit behavior simulation - are defined. Joint simulation of a circuit synthesized from STG with its environment is also presented.
Keywords: VHDL, Verilog HDL, interpreted Petri nets, timed signal transition graphs.
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