In: Proceedings of the Seventh International Workshop on Petri Nets and Performance Models, June 3-6, 1997, Saint Malo, France, pages 153-162. Los Alamitos, California: IEEE Computer Society, June 1997.
Abstract: Multithreaded distributed-memory multiprocessor architectures are composed of a number of (multithreaded) processors, each with its memory, and an interconnection network. The long memory latencies and unpredictable synchronization delays are tolerated by context switching to processor to another `ready' thread provided such a thread is available. Because of very simple representation of concurrency and synchronization, timed Petri net models seem to be well suited for modeling and evaluation of such architectures. However, accurate net models of multi-threaded multiprocessors become quite complicated, so their analysis can be a nontrivial task. This paper describes a timed colored Petri net model of a multithreaded multiprocessor architecture, and presents some results obtained by simulation of this model. A simplified approach to modeling such architectures is also proposed.