In: Digest of Technical Papers ot the IEEE International Conference on Computer-Aided Design, 1989, Santa Clara, CA, USA, pages 172-175. Los Alamitos, CA, USA: IEEE Comput. Soc. Press, 1989.
Abstract: The authors discuss methodologies and tools that allow a system to be analyzed using Petri nets or queuing models. Such analysis is performed early in the design process to evaluate overall system performance. Different methodologies and tools are available to allow design analysis and verification at interpreted levels through hardware design language (HDL) descriptions. The methodology presented allows the designer to create uninterpreted models in an environment already capable of interpreted modeling, the VHSIC hardware description language (VHDL).
Keywords: VHSIC hardware description; very high speed IC; queueing model; hardware description language VHDL.