In: 33. internationales wissenschaftliches Kolloquium: Mathematische Optimierung, Theorie und Anwendungen, 1988, Ilmenau, DDR, pages 191-194. 1988.
Abstract: In this paper a new approach to the modelling and faults detection in CMOS cells is presented. For the purposes of testing the cells are modelled by means of Petri nets. The Petri net model is formed on the basis of its electrical diagram. The paper describes the modelling of classical stuck-at, bridgeing faults and nonclassical logical faults, like stuck-open, using Petri nets. These non-classical faults are characteristis of CMOS technology.