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System level testability analysis using Petri nets.

Jiang, T.; Aylor, J.H.; Han, G.

In: Proc. IEEE Int. High-level Design Validation and Test Workshop, 8-10 November 2000, Berkeley, CA, pages 112-117. 2000.

Abstract: The test problem increasingly affects system design costs. One approach to reducting testing difficulties is to consider system testability as early as possible in the design cycle. The technique described here adds a testability analysis capability to the ADEPT high-level performance modeling environment. This capability provides the designer with feedback on the testability of the specific architecture being modeled at an abstract level. The testability information is expressed in the form of measures of relative controllability and servability of signals in the system architecture. The testability information is derived from reachability graph analysis of the corresponding Petri net representation of the system architecture. This methodology has the potential to provide valuable assistance in designing systems which have lower cost, higher performance, and which also meet testability requirements.

Keywords: ADEPT, Petri nets, performance modeling, system-level testability.

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