In: Concurrency and Hardware Design, pages 34-60. Advances in Petri Nets, Volume 2549 of Lecture Notes in Computer Science / J. Cortadella, A. Yakovlev, G. Rozenberg (Eds.) --- Springer Verlag, November 2002.
Abstract: Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchronous logic block is to interact with its environment. Using the tool di2pn, such a specification can be automatically translated into a Petri net. Using the tool petrify, the net can be automatically validated (for freedom from deadlock and interference, and for implementability as a speed-independent circuit) and asynchronous logic can be automatically synthesised.