In: Proceedings of Design Automation Conference, 41st Conference on (DAC'04), June 07 - 11, 2004, San Diego, California, USA, pages 830-833. IEEE Press, June 2004.
Abstract: Synthesis of asynchronous logic using the tool Petrify requires a state graph with a complete state coding. It is common for specifications to exhibit concurrent outputs, but Petrify is sometimes unable to resolve the state coding conflicts that arise as a result, and hence cannot synthesise a circuit. A pair of decomposition heuristics (expressed in the language of Delay-Insensitive Sequential Processes) are given that helps one to obtain a synthesisable specification. The second heuristic has been successfully applied to a set of nine benchmarks to obtain significant reductions both in area and in synthesis time, compared with synthesis performed on the original specifications.
Keywords: Asynchronous logic synthesis; delay-insensitive decomposition.