In: FTCS 19: Proceedings of The Nineteenth International Sympsoium on Fault-Tolerant Computing, 1989, Chicago, IL, USA, pages 545-552. Washington, DC, USA: IEEE Comput. Soc. Press, 1989.
Abstract: The problem of modeling fault-tolerant processor arrays is addressed, and a systematic method to construct Markov models for evaluating the reliability is proposed. This method is based on the premise that the fault behavior of a processor array can be modeled by a stochastic Petri net. However, in order to obtain a more compact representation, a set of attributes is associated with each transition in the Petri net model. Included in these attributes is a discrete probability distribution such that the effect of faulty spares in the reconfiguration algorithm is captured each time a configuration change occurs.
Keywords: fault-tolerance; processor arrays; stochastic net; transition attribute; discrete probability distribution; reliability.
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