In: Igls, Austria: Procs. of the VHDL-Forum for CAD in Europe, Innsbruck, pages 58-68. 1993.
Abstract: In this paper we consider the VHDL language through an unusual point of view, which is its execution model. We compare the VHDL delay model with other delay models, zero and unit delay. We deal also with the determinism of the language VHDL and clarify some missunderstandings about this topic.
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