In: Proceedings of the Second European Conference on VHDL Methods (EURO-VHDL'91), Stockholm, Sweden, pages 1-10. 1991.
Abstract: This paper presents a method for detecting bad behaviours (e.g. deadlocks) in VHDL programs using structural analysis techniques of Petri nets. The translation of the VHDL programs into Petri nets that preserve control flow and signal flow properties are described. Petri net invariants are used to analyze the existence of deadlocks in the program. Last we present an example on which we illustrate this approach.
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