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Parallel controller synthesis for programmable logic devices.

Pardey, J.; Amroun, A.; Bolton, M.; Adamski, M.

In: Microprocessors and Microsystems, Vol. 18, No. 8, pages 451-457. 1994.

Abstract: The standard approach to parallel controller design uses sequential controller design techniques. However, since these techniques cannot represent concurrent states, the problem must first be partitioned and then designed as a number of linked finite state machines. This initial partitioning is usually non-optimum and limits the amount of concurrency in the subsequent design, where the interaction between the finite state machines also makes verification difficult. This paper presents an alternative technique for parallel controller design in which a synchronous, interpreted Petri net is used to model the controller's specification as a single parallel network. No pre-partitioning is necessary, and the amount of concurrency dynamically reflects the amount of parallel activity on the data path. The formalism provided by the technique also reduces the likelihood of parallel synchronization errors. The technique is illustrated with the design of a parallel controller for a transputer link adapter and its implementation on a programmable logic device.

Keywords: interpreted Petri nets, parallel controllers, programmable logic devices.

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