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What is the cost of delay insensitivity?.

Saito, H.; Kondratyev, A.; Cortadella, J.; Lavagno, L.; Yakovlev, A.

In: Proc. 2nd Workshop on Hardware Design and Petri Nets (HWPN'99) of the 20th Int. Conf. on Application and Theory of Petri Nets (PN'99), 21 June 1999, Williamsburg, VA, pages 169-189. 1999.

Abstract: Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical. The paper presents an approach for automated synthesis of globally DI and locally SI circuits. It is based on order relaxation, a simple graphical transformation of a circuit's behavioral specification, for which signal transition graph, an interpreted Petri nets, is used. The method is successfully tested o a set of benchmarks and a realistic design example. It proves effective showing average cost of DI interfacing at about 40 percent for area and 20 percent for speed.

Keywords: asynchronous circuit design, delay insensitivity, interpreted Petri nets, signal transition graphs, submicron technologies.

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