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Validation of a VLSI Chip Using Hierarchical Colored Petri Nets.

Shapiro, R.M.

In: Microelectronics and Reliability, Vol. 31, No. 4, pages 607-625. 1991.

Abstract: The paper focuses on the task of modelling and validating the behavior of a VLSI chip using hierarchical Colored Petri Nets (CPNs). The author describes an approach whereby engineering block diagrams, supplemented with suitable formal inscriptions can be mapped directly to a CPN model. He shows in detail a CPN model of an actual digital filter chip from a super-computer. The author describes the potential of using formal analysis methods and proposes a simplification technique for reducing the combinatorics involved in Occurrence Graph Analysis. Performance issues are discussed and an extension to Colored Petri Nets that incorporates the concept of time is proposed.

Keywords: validation (of) VLSI chip (using) hierarchical coloured net(s); register transfer level; engineering block diagram; digital filter chip; occurrence graph; performance; timed coloured net.


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