In: Proceedings of the 11th International Conference on Application and Theory of Petri Nets, 1990, Paris, France, pages 224-243. 1990.
Abstract: In this paper the author focuses on the task of modelling and validating the behavior of a VLSI chip using hierarchical Colored Petri Nets (CPNs). The author discusses current pratice in hardware design at the register transfer level. An approach is described whereby engineering block diagrams can be mapped directly to a CPN model. A CPN model of an actual digital filter chip from a super-computer is shown in detail. The author describes the potential of using formal analysis methods and proposes a simplification technique for reducing the combinatorics involved in Occurrence Graph Analysis.
Keywords: VLSI chip validation; hierachical coloured net; digital filter; occurrence graph analysis.