In: Proceedings of the 10t Annual International Phoenix Conference on Computers and Communications, 1991, Scottsdale, AZ, USA, pages 3-9. Piscataway, NJ, USA: IEEE Service Center, 1991.
Abstract: The authors are concerned with performance modeling and enhancement for periodic execution of large-grain, decision-free algorithms in data flow architectures operating in real-time. The mapping of real-time algorithms onto data flow architectures is realized by a marked graph model called ATAMM (algorithm to architecture mapping model). Applications include control, surveillance, and signal processing problems. Performance is characterized by computing speed and throughput. Bounds on performance measures are established. A technique for transforming an algorithm to improve throughput while maintaining input-output equivalence is presented.
Keywords: performance modelling; real-time data flow architecture; marked graph model ATAMM, algorithm (to) architecture mapping model; control; surveillance; signal processing.