In: IEEE Design Automation Conference, 1989, Las Vegas, NV, USA: Proceedings of the 26th ACM, pages 738-741. New York, NY, USA: ACM, 1989.
Abstract: A novel applicative model is presented for the description and analysis of both synchronous and asynchronous VLSI networks at the top levels of abstraction. The model is based on the applicative state transition (AST) concept for the descriptive aspects and the theory of single token time(d) Petri nets for the communicative aspects of the model. The model allows the description of self-timed systems, synchronous systems, and combinational ripple logic from the highest functional level onto the register transfer level. The model favors a hierarchical design style of stepwise structural refinement of behavioral descriptions.
Keywords: high level description; VLSI; applicative state transition concept, AST; timed net; self-timed system; hierarchical design.
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