In: Yakovlev, A.; Gomes, L.: Proceedings of the Workshop on Hardware Design and Petri Nets (HWPN'98). Lisbon, Portugal, 1998.
Also in: Yakovlev, A.; Gomes, L.; Lavagno, L.: Hardware Design and Petri Nets, pages 269-289. Boston: Kluwer Academic Publishers, 2000.
Abstract: We present an approach to model dataflow architectures at a high level of abstraction using timed coloured Petri nets. We specifically examine the value of Petri nets for evaluating the performance of such architectures. For this purpose we assess the value of Petri nets both as a modelling technique for dataflow architectures and as an analysis tool that yields valuable performance data for such architectures through the execution of Petri net models. Because our aim is to use the models for performance analysis, we focus on representing the timing and communication behaviour of the architecture rather than the functionality. A modular approach is used to model architectures. We identify five basic hardware building blocks from which Petri net models of dataflow architectures can be constructed. In defining the building blocks we will identify strengths and weaknesses of Petri nets for modelling dataflow architectures. A technique called folding is applied to build generic models of dataflow architectures. A timed coloured Petri net model of the Prohid dataflow architecture, which is being developed at Philips Research Laboratories, is presented. This model has been designed in the tool ExSpect. The performance of the Prophid architecture has been analysed by simulation with this model.
Keywords: dataflow architectures, hardware modelling, performance analysis, Petri nets.
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