In: Proc. 2nd Workshop on Hardware Design and Petri Nets (HWPN'99) of the 20th Int. Conf. on Application and Theory of Petri Nets (PN'99), 21 June 1999, Williamsburg, VA, pages 35-62. 1999.
Also in: Yakovlev, A.; Gomes, L.; Lavagno, L.: Hardware Design and Petri Nets, pages 239-268. Boston: Kluwer Academic Publishers, 2000.
Abstract: This paper describes and extends a recently developed approach for performance analysis of asynchronous circuits modeled with stochastic timed Petri nets (STPNs) with unique and free-choice places and arbitrary delay distributions. The approach analyzes finite STPN executions to derive closed-form expressions for lower and upper bounds on the performance estimates that can be efficiently evaluated using standard statistical methods. The mean of the derived upper and lower bounds provides an estimate of the performance metric which has a well-defined error interval. Moreover, the error interval can always be made arbitrarily small by analyzing longer STPN executions at the cost of additional run times. Experiments on several asynchronous systems demonstrate the high quality of the estimates and the efficiency of the technique. The experiments include the performance analysis of a full-scale Petri net model of Intel's asynchronous instruction length decoding and steering unit RAPPID containing over 900 transitions and 500 places.
Keywords: RAPPID, asynchronous circuits, asynchronous systems, performance analysis, stochastic timed Petri nets.