In: E-Commerce: FORTE 2004 Workshops The FormEMC, EPEW, ITM, Toledo, Spain, October 1-2, 2004: Proceedings of Applying Formal Methods: Testing, Performance, and M, pages 209-219. Volume 3236 of Lecture Notes in Computer Science / Manuel Núñez, Zakaria Maamar, Fernando L. Pelayo et al. (Eds.) --- Springer-Verlag, September 2004.
Abstract: Instruction level multithreading is a technique for tolerating long-latency operations (e.g., cache misses) by switching the processor to another thread instead of waiting for the completion of a lengthy operation. In block multithreading, context switching occurs for each initiated long-latency operation. However, processor cycles during pipeline stalls as well as during context switching are not used in typical block multithreading, reducing the performance of a processor. Dual block multithreading introduces a second active thread which is used for instruction issuing whenever the original (main) thread becomes inactive. Dual block multithreading can be regarded as a simple and specialized case of simultaneous multithreading when two (simultaneous) threads are used to issue instructions for a single pipeline. The paper develops a simple timed Petri net model of a dual block multithreading and uses this model to estimate the performance improvements of the proposed dual block multithreading.
Keywords: Block multithreading; instruction issuing; pipelined processors; timed Petri nets; performance analysis; event-driven simulation.