In: Proc. 2nd Workshop on Hardware Design and Petri Nets (HWPN'99) of the 20th Int. Conf. on Application and Theory of Petri Nets (PN'99), 21 June 1999, Williamsburg, VA, pages 63-82. 1999. Available at ftp://ftp.cs.mun.ca/pub/publications/99-HWPN.ps.Z.
Also in: Yakovlev, A.; Gomes, L.; Lavagno, L.: Hardware Design and Petri Nets, pages 311-331. Boston: Kluwer Academic Publishers, 2000.
Abstract: In multithreaded distributed memory architectures, long-latency memory operations and synchronization delay are tolerated by suspending the execution of the current thread and switching to another thread, which is executed concurrently with the long-latency operation of the suspended thread. Timed Petri nets are used to model several multithreaded architectures at the instruction and thread levels. Model evaluation results are presented to illustrate the influence of different model parameters on the performance of the system.
Keywords: distributed memory architectures, multithreaded architectures, performance modeling, timed Petri nets.