In: Proceedings of Fourth International Conference on Application of Concurrency to System Design (ACSD'04), June 16 - 18, 2004, Hamilton, Ontario, Canada, pages 7-15. IEEE Press, June 2004.
Abstract: In interleaved multithreading, the thread changes in each processor cycle, consecutive instructions are issued from different threads, and no data dependencies can stall the pipeline. Enhanced inteleaved multithreading maintains a number of additional threads which are used to replace an active thread when it initiates a long-latency operation. Instruction issuing slots, which are lost in pure interleaved multithreading, are thus used by instructions from the new thread. The paper studies performance improvements due to enhanced multithreading by analyzing a timed Petri net model of an enhanced multithreaded architecture at the instruction execution level.
Keywords: Interleaved multithreaded architectures; distributed-memory multiprocessors; timed Petri nets; performance analysis; event-driven simulation.