In: Proc. 16th Performance Engineering Workshop, 24-25 July 2000, Durham, UK, pages 187-198. 2000.
Abstract: In block multithreaded processors, instruction dependencies occasionally stall the pipeline for one or more processor cycles. The paper uses a timed Petri net model of a multithreaded multiprocessor to study the influence of pipeline stalls on the performance of processors. Presented results are obtained by simulation of the net model.
Keywords: block multithreaded processors, performance analysis, pipeline stalls, timed Petri nets.