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The design of the control circuit for an asynchronous instruction prefetch unit using signal transition graphs.

Chung, S.-H.; Farber, S.B.

In: Proc. 2nd Workshop on Hardware Design and Petri Nets (HWPN'99) of the 20th Int. Conf. on Application and Theory of Petri Nets (PN'99), 21 June 1999, Williamsburg, VA, pages 131-147. 1999.

Also in: Yakovlev, A.; Gomes, L.; Lavagno, L.: Hardware Design and Petri Nets, pages 171-190. Boston: Kluwer Academic Publishers, 2000.

Abstract: AMULET3 is the third fully asynchronous implementation of the ARM architecture designed at the University of Manchester. It implements the most recent version of the ARM architecture (V4T), including the Thumb instruction set. Significant architectural changes from its predecessors help achieve high performance without sacrificing the advantages of asynchronous design. One of these changes is to incorporate a highly parallel instruction prefetch unit. This paper introduces the instruction prefetch unit in AMULET3, highlighting where speed-independent control circuits are implemented using signal transitions graphs (STGs). In order to show how control circuits are implemented in the instruction prefetch unit of AMULET3, several examples are presented with relevant STGs and the synthesized circuit results.

Keywords: AMULET3, ARM architecture, Thumb instruction set, asynchronous circuits, instruction prefetch units, signal transition graphs.

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