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Modeling, qualitative-analysis, and performance evaluation of the etching area in an IC wafer fabrication system using Petri nets.

Jeng, M.D.; Xie, X.L.; Chou, S.W.

In: IEEE Trans. on Semiconductor Manufacturing, Vol. 11, No. 3, pages 358-373. 1998.

Abstract: Integrated circuit (IC) wafer fabrication systems can be characterized as discrete event systems, Petri nets are tools that have been successfully used to model and analyze such systems. This paper reports a project of applying Petri net methodologies to detailed modeling, qualitative analysis, and performance evaluation of the etching area in a real-world IC wafer fabrication system located in Taiwan's Hsinchu Science-Based Industrial Park. To tackle the problem of building a large and complex system model, a synthesis technique is used. The resultant extended net model is checked for important qualitative properties in manufacturing, A simple control policy for deadlock prevention is proposed. To obtain performance measures, simulation is used. The simulation result shows that except a small number of machines, the errors between the simulated and actual utilizations are less than 5%. The validated model can be used to answer many `what-if' questions, such as predicting the maximal throughput and bottleneck machines.

Keywords: Petri nets, deadlock prevention, discrete-event systems, etching area, performance evaluation, semiconductor manufacturing, simulation techniques, wafer fabrication.

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