In: IEICE Trans. on Fundamentals in Electronics, Communications and Computer Science, Vol. E78-A, No. 11, pages 1504-1510. 1995.
Abstract: An approach to derive a logic function of asynchronous circuits from a graph-based model called signal transition graph (STG) is described. STGs are Petri nets whose transitions are interpreted as a signal transition on the circuit inputs or gate outputs, and its marking represents a binary state of the circuit. STGs can represent a behavior of circuit; to derive logic functions, however, the reachability graph should be constructed. In the verification of STGs, some method based on occurrence nets and its prefix, called unfolding, has been proposed. Occurrence nets can represent both causality and concurrency between two nodes by net structure. This paper proposes a method to derive a logic function be generating substate space of a given STG using the structural properties of occurrence nets. The proposed method can be seen as a parallel algorithm for deriving a logic function.
Keywords: asynchronous circuits, occurrence nets, signal transition graphs, state space explosion.