In: IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 6, pages 769-786. 1999.
Abstract: This paper presents a new algorithm for timed state-space exploration, POSET timing. POSET timing improves upon geometric methods by utilizing concurrency and causality information to dramatically reduce the number of geometric regions needed to represent the timed state space. The utility of POSET timing is illustrated by its application to the automatic synthesis and verification of gate-level timed circuits. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize the design. Using POSET timing, the synthesis procedure derives a timed circuit that is hazard-free. The circuit uses only basic gates to facilitate the mapping to semi-custom components, such as standard-cells and gate-arrays. The resulting gate-level timed circuit implementations are 30 to 40 percent smaller and 30 to 50 percent faster than those produced using other asynchronous design methodologies. This paper also demonstrates that timed design can be smaller and faster than their synchronous counterparts. The POSET timing algorithm can not only efficiently verify the synthesized circuits but also a wide collection of large, highly concurrent timed circuits and systems that could not be previously be verified using traditional techniques. POSET timing verification can be used to a general class of specifications which can be translated into a one-safe timed Petri net.
Keywords: POSET timing, formal verification, geometric regions, logic synthesis, partial orders, timed Petri nets, timed asynchronous circuits.