In: Procs of the First Asian Pacific Conference on Hardware Description Languages, Standards and Applications (APCHDLSA'93), Brisbane, QLD, Australia, pages 71-75. 1993.
Abstract: This paper describes a framework for automated static analysis of VHDL based on Petri Nets. The environment provides facilities for analysis and simulation. The approach is based on a formal model of the VHDL simulation semantics. Some tools implementing this approach are currently under development in FORMAT project (CEC ESPRIT III project 6128).
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