In: Procs. of the Euro-VHDL'93 Conference, CCH Hamburg, Germany, pages 526-531. IEEE Computer Society Press, 1993.
Abstract: There exists a stron necessity for a formal interpretation of VHDL. This paper address this aspect. The formal model used for this purpose are Coloured Petri nets because can cover all aspects of VHDL. We start from the underlying executable model of VHDL based on communicating processes. The formal model of a VHDL description results from the specification in Petri net terms of the user-defined processes, the kernel process (VHDL simulator) and the communicating links between them. This approach can also be applied to other HDLs with the same underlying paradigm.
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