In: IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, pages 1108-1129. 1998.
Abstract: Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal transitions. The synthesis of concurrent systems implies the analysis of a vast state space that often requires computationally expensive methods. This work presents new methods for the synthesis of speed-independent circuits from a new perspective, overcoming both the analysis and computation complexity bottlenecks. The circuits are specified by free-choice signal transition graphs (STG's), a subclass of interpreted Petri nets. The synthesis approach is divided into the following steps: correctness, binary coding, implementability conditions, and logic synthesis. Each step is efficiently implemented by applying a set of structural techniques that analyze STG's without explicitly enumerating the underlying state space. Experimental results show that circuits can be generated from specifications that exceed in several orders of magnitude the largest STG's ever synthesized. Computation times are also dramatically reduced. Nevertheless, the quality of results does not suffer from the use of structural techniques.
Keywords: Petri nets, asynchronous circuits, speed-independent synthesis.