In: Microprocessing and Microprogramming, Vol. 30, No. 1--5; Proceedings of the Sixteenth EUROMICRO Symposium on Microprocessing and Microprogramming (EUROMICRO 90), 1990, Amsterdam, The Netherlands, pages 313-319. August 1990.
Abstract: This paper presents a method for realizing random logic circuit implementations of Timed Petri Nets. Timed Petri Nets have been shown to be effective methods of describing concurrent behaviour of hardware systems, and allow transformations to be applied to optimize a design specification given a set of constraints such as cost and time. The presented method of implementation requires delay free Timed Petri Nets, and a synchronous interpretation of the firing of transitions. The actual realization is achieved by first applying a one-to-one mapping to a generic hardware cell, and second reducing unnecessary gate logic through a set of simple transformation rules.
Keywords: random logic circuit implementation (of) extended delay free timed net; cost (and) time constraint; gate logic.