Technical Report 87--29, pages 1-13 pp.. Irvine, USA: University of California; Department of Information and Computer Science, December 1987.
Abstract: This paper discusses the use of Petri nets for modeling and analyzing pipelined processors. Petri nets are particularly well-suited to modeling synchronization, buffering, resource contention and delicate timing so common in pipelined processors. Tools for simulating, animating and analyzing the behavior of the models are described. The usefulness of the tools and the analysis methods they support in evaluating the performance and analyzing the detailed timing of pipelined microprocessors is illustarded through an example.
Keywords: modeling pipelined processors; resource contention; performance evaluation; microprocessor.