In: Proceedings of the Ninth Annual International Phoenix Conference on Computers and Communications, 1990, Scottsdale, AZ, USA, pages 163-169. Piscataway, NJ, USA: IEEE Service Center, 1990.
Abstract: The algorithm-to-architecture mapping model (ATAMM) is a new marked graph model from which the rules for data and control flow in a homogeneous, multicomputer, data-flow architecture may be defined. This study is concerned with performance modeling for periodic execution of large-grain, decision-free algorithms in such an ATAMM-defined architecture. The computing environment, problem domain, and algorithm execution pattern are described. Performance measures of computing speed and throughput capacity are defined. Performance bounds are established. Resource needs are determined for periodic execution of algorithms.
Keywords: performance modelling (for the) ATAMM data flow architecture; algorithm (to) architecture mapping model; multicomputer, data flow architecture; marked graph; throughput capacity; periodic execution.