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A Model for the High-Level Description and Simulation of VLSI Networks.

van der Hoeven, A.J.; de Lange, A.A.J.; Deprettere, E.F.; Dewilde, P.M.

In: IEEE Micro, Vol. 10, No. 4, pages 41-48. August 1990.

Abstract: An applicative state transition (AST) model for the description and analysis of synchronous and asynchronous VLSI networks at the top levels of abstraction is presented. The model explicitly represents the flow of information through a network. This is done by embedding the AST concept into the theory of Petri nets and using Petri net theory to define the communication protocol between nodes. As an application the design of a simple priority queue as both a real-time systolic (synchronous) system and a real-time wavefront (asynchronous) system is explored. The model has been embedded in an interactive design system called HIFI.

Keywords: VLSI, description, simulation; applicative state transition (model); communication protocol; priority queue; systolic system; HIFI, interactive design.

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