Technical Report 609. Rehorot, Israel: TECHNION, Israel Institute of Technology, Computer Science Department, February 1990.
Abstract: This paper is an introduction to a novel formal theory of delay-insensitive circuits, their verification and synthesis. The author considers asynchronous circuits, obtained by suitable interconnecting basic components (modules). The novel features of this approach are the following: (1) A suitable formal delay and race model is developed; (2) In a new way the concept ``implementation satisfies specification'' is defined; (3) Petri nets are used for both the high-level specifications as well as the synthesis of delay-insensitive circuits --- The synthesis method derived in this paper is restricted to certain classes of Petri nets; research is in progress to expand the applicability of this approach.
Keywords: net-based synthesis (of) delay-insensitive circuit; modular approach; high level net specification.
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